A parallel channel bit error rate tester is normally used in communication systems having a number of separate channels. Such testers provide a means for testing many channels simultaneously, and hence, reduce the time needed to test a communication system. In addition, such testers can detect errors that are only present when a number of channels are operating simultaneously. For example, errors resulting from cross-talk between two channels only appear when there is data on both channels. A parallel channel bit error rate tester typically includes a pattern generator for generating signals on each of the channels to be tested and an analyzer that examines the signals received at the terminus of the communication channels to determine if the received signals match the generated signals from the pattern generator.
A parallel channel bit error rate tester may also be used to test a communications channel having a data rate that is higher than that of the individual channels of the tester. To do this, individual test signals from the pattern generator channels are multiplexed together to form a high-speed signal which is sent on the high-speed channel. At the terminus of the communication channel, the high speed data stream is demultiplexed and fed to the error analyzer channels of the parallel channel bit error rate tester.
The multiplexer and demultiplexer circuits may be considered part of the instrument or part of the device under test (DUT), depending upon the application. For example, communication systems in which a number of relatively low speed signals are multiplexed to form a single high-speed signal that is sent on a high-speed link and then demultiplexed are well known in the communication arts. In such systems, the parallel channel bit error rate tester need not include the multiplexers and demultiplexers, as these are part of the communications system that is being tested. On the other hand, if the communications system being tested has only one input and output channel, the multiplexers and demultiplexers must be provided as part of the testing system to test the high-speed link.
The conversion of parallel streams into a serial stream and then back into parallel streams via multiplexers and demultiplexers can lead to a rearrangement of the data patterns such that the pattern input on the ith channel of the transmitting device is not received on the ith channel of the receiver. This can occur if the phases of the various multiplexers and demultiplexers are not properly synchronized. This lack of synchronization can result from the multiplexers not being synchronized with each other, the demultiplexers not being synchronized with each other, or the demultiplexers as a group not being synchronized with the multiplexers as a group. An unknown time delay through the communication link often results in a lack of synchronization between the multiplexers and the demultiplexers. Each of these conditions can result in a rearrangement of the data patterns.
These data rearrangements pose a problem because bit error-rate testing is based on knowledge of the data pattern expected in each channel by the error analyzer. If the expected data pattern is rearranged, then the test is useless unless this rearrangement can be identified. Once identified, the appropriate compensation can be instituted.
In principle, the rearrangements can be removed by synchronizing the multiplexer circuits with each other, and/or synchronizing the demultiplexer circuits with each other, and then synchronizing the multiplexer circuits to the demultiplexer circuits. At that point, the data streams entering the analyzer can be synchronized with each other in time. While communications multiplexers that are synchronized to each other (and also have synchronized phases) can be constructed, it is far less practical to construct communications demultiplexers that can be synchronized to each other and share a common internal phase. This is largely due to two phenomena. First, demultiplexers often recover the data clock from the data passing therethrough. The clock recovery circuits in these demultiplexers have divide by n circuits, where n is the fan out of the demultiplexer. These circuits typically initialize in a random state relative to the multiplexers, and hence, will not, in general, be properly synchronized. Secondly, the unavoidable time delay of propagating the data stream through the communication link connecting the multiplexers and demultiplexers results in the data arriving with an unknown phase relative to that of the multiplexers.
Broadly, it is the object of the present invention to provide an improved parallel channel bit error rate tester and method of using the same to test communications networks, and the like.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.